Recent Changes

Thursday, March 24

  1. 7:34 am
  2. page Waveform Generator edited ... Det giver ikke mening at programmere kredsen med AudioData porten på, da vi ikke har noget at …
    ...
    Det giver ikke mening at programmere kredsen med AudioData porten på, da vi ikke har noget at forbinde den til. Det er udelukkende til at debugge med.
    I næste øvelse, kommer vi til at forbinde outputtet sammen med det codec interface som vi skal lave der. Vi forsøger derved at få den genererede tone ud på DE2 boardets line-out stik og ud i et par hørebøffer.
    Beregning af Prescaler
    {2011-03-24_15.26.30.jpg}

    (view changes)
    7:34 am
  3. 7:33 am
  4. page Exercises_WaveformGenerator edited ... {vdl2_ex7_block.jpg} The output signal is generated by looping thru the ROM. The pace used, …
    ...
    {vdl2_ex7_block.jpg}
    The output signal is generated by looping thru the ROM. The pace used, sets the output frequency.
    ...
    fixed amount (prescaler),(prescaler) of four, and then
    Fwaveform = Faddress / Nsamples = Fsystem / (Nsamples * Prescaler * WF.FREQ)
    Example: Fwaveform = 12 MHz / (180 * 4 * 16 samples) = 1041 Hz
    (view changes)
    3:15 am

Wednesday, March 23

  1. page Exercises_WaveformGenerator edited ... One process creates the CounterEnable signal, by dividing the 12MHz clock. The divider is the …
    ...
    One process creates the CounterEnable signal, by dividing the 12MHz clock. The divider is the sum of the pre-scaler value and WF_FREQ register (but use a constant for now!).
    The second process must contain a circular counter that increments, when CountEnable is high. The count value is to be used for selecting the ROM address input.
    ...
    signal for the
    processes,
    theprocesses, you must
    Use the supplied testbench to simulate that the counter works.
    Create a “ROM: 1-PORT” component using the MegaWizard. It must be 24 bits wide and contain 256 words. Don’t use an output register (q), and specify a memory content file : “SinusiodROM.hex”. See the guidelines in the Wiki.
    (view changes)
    1:47 pm
  2. page Exercises_WaveformGenerator edited ... Step 1: Create the basic Waveform Generator Use the WaveforGenerator design-entity provided. …
    ...
    Step 1: Create the basic Waveform Generator
    Use the WaveforGenerator design-entity provided. Create the two processes shown in the figure above:
    ...
    for now!).
    The

    The
    second process
    ...
    address input.
    The

    The
    processes must
    ...
    for the processes,
    processes,
    you must
    Use the supplied testbench to simulate that the counter works.
    Create a “ROM: 1-PORT” component using the MegaWizard. It must be 24 bits wide and contain 256 words. Don’t use an output register (q), and specify a memory content file : “SinusiodROM.hex”. See the guidelines in the Wiki.
    ...
    In Quartus, create a new clock in Assignments->Settings->Classic Timing Analyzer..-> Individual Clocks. Create a new clock setting. Pick “Clk” pin in the node finder, and set the required Fmax = 50MHz.
    Run Compilation, and view the timing report afterwards. You will probably get timing errors on the signals crossing the clock domain in the WaveformGenerator, namely WF_FREQ and WF_FREQ_avs and the same for WA_ATT.
    {vdl2_ex7_timing_error.jpg}
    To tell the analyzer that we allow the signals to take multiple clock cycles to settle, we have to specify the “multicycle” assignment for the two registers in the assignment editor. Set the value to “2”. And pick the in- / outputs in the node finder.
    {vdl2_ex7_multicycle_assignment.jpg}
    Re-run compilation, this time it should be successful
    You will not be able to test the design on your board yet! (We need the codec to get it to work)
    (view changes)
    1:25 pm
  3. page Exercises_WaveformGenerator edited Introduction ... to generate a digital sinusoid waveforms. These waveform. The waveform ge…

    Introduction
    ...
    to generate a digital sinusoid waveforms. Thesewaveform. The waveform generator will be used as a tone generator for input to later signal
    ...
    exercises. The waveform generator contains two registers accessible by means of the Avalon-MM bus, these registers allow manipulation of the sinusoid frequency and amplitude can be changed using two registers. Theamplitude.
    The
    waveform is
    ...
    table in a ROM memory
    ...
    predefined values.
    A

    To speed up the design process, a
    template design
    ...
    of the existing).existing files).
    Goal
    Create a waveform generator to generate tones for later signal processing and audio interfacing exercises.
    Get experience with PLLs, clocks and clock domains
    Get even more experience with test benches and simulation
    Design
    The design is build around a ROM containing a normalized sinusoid. The values are 24-bit, 2’s complement, which is commonly used for digital audio.
    {vdl2_ex7_block.jpg}
    The output signal is generated by looping thru the ROM. The pace used, sets the output frequency.
    The address counter is fed by the system clock and a clock enable signal generated by a clock divider. The system clock is first divided by a fixed amount (prescaler), and then by the value given in the WF.FREQ register:
    Fwaveform = Faddress / Nsamples = Fsystem / (Nsamples * Prescaler * WF.FREQ)
    Example: Fwaveform = 12 MHz / (180 * 4 * 16 samples) = 1041 Hz
    The ROM initialization file provided contains a sinusoid with 180 samples (Nsamples = 180). A good choice for the pre-scaler is 4.
    Exercises
    Step 1: Create the basic Waveform Generator
    Use the WaveforGenerator design-entity provided. Create the two processes shown in the figure above:
    One process creates the CounterEnable signal, by dividing the 12MHz clock. The divider is the sum of the pre-scaler value and WF_FREQ register (but use a constant for now!).
    The second process must contain a circular counter that increments, when CountEnable is high. The count value is to be used for selecting the ROM address input.
    The processes must use the 12MHz clock signal as this is the clock source for the audio sub-system. If you need a reset signal for the processes, you must consider the how to let the csi_clockreset_reset_n signal pass to the 12MHz clock domain.
    Use the supplied testbench to simulate that the counter works.
    Create a “ROM: 1-PORT” component using the MegaWizard. It must be 24 bits wide and contain 256 words. Don’t use an output register (q), and specify a memory content file : “SinusiodROM.hex”. See the guidelines in the Wiki.
    Add the ROM to the project and instantiate it in the WaveforGenerator entity. Connect the ROM address to the counter output.
    Simulate! In the waveform window change the “radix” to “decimal” and “format” to “analog” for the ROM output signal. You should be able to see a sinusoidial waveform!
    Step 2: Use registers to regulate frequency and attenuation
    Create the functionality of the two registers: Waveform Frequency Register and Waveform Annutation Register. See the wiki page for the required functionality. The interface to the Avalon-MM bus and the storage of the the values is already implemented in the template file.
    Use the value of the WF_FREQ register to set the value in the clock divider.
    Use the WA_ATT value to attenuate the AudioData signal. Hint! Use “shift_right” and “signed” (signed because the waveform is 2’s complement).
    Run simulation again and verify that the default values are used.
    Step 3: Compile it in Quartus
    In Quartus, create a new clock in Assignments->Settings->Classic Timing Analyzer..-> Individual Clocks. Create a new clock setting. Pick “Clk” pin in the node finder, and set the required Fmax = 50MHz.
    Run Compilation, and view the timing report afterwards. You will probably get timing errors on the signals crossing the clock domain in the WaveformGenerator, namely WF_FREQ and WF_FREQ_avs and the same for WA_ATT.
    To tell the analyzer that we allow the signals to take multiple clock cycles to settle, we have to specify the “multicycle” assignment for the two registers in the assignment editor. Set the value to “2”. And pick the in- / outputs in the node finder.
    Re-run compilation, this time it should be successful
    You will not be able to test the design on your board yet! (We need the codec to get it to work)

    (view changes)
    1:08 pm
  4. page Registers & Memory Map edited ... Registers Waveform Generator Waveform WAWaveform Attenuation Register, BIT 7 ... Wav…
    ...
    Registers
    Waveform Generator
    WaveformWAWaveform Attenuation Register,
    BIT
    7
    ...
    Waveform_out = Waveform_in / ATT
    Only attenuations dividable by two is allowed, that is, bit 0 is always read as zero.
    abcWaveformWFWaveform Frequency Register,
    BIT
    7
    ...
    If FREQ = 0, then FREQ=0x10, is used.
    Codec Interface
    CodecCICodec Init Register,
    BIT
    7
    (view changes)
    12:58 pm
  5. page Registers & Memory Map edited ... Waveform_out = Waveform_in / ATT Only attenuations dividable by two is allowed, that is, bit …
    ...
    Waveform_out = Waveform_in / ATT
    Only attenuations dividable by two is allowed, that is, bit 0 is always read as zero.
    WaveformabcWaveform Frequency Register,
    BIT
    7
    (view changes)
    12:51 pm
  6. 12:33 pm

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