Exercises_SequentialTestBench

=Introduction=

For our AMVE we need an emulator to let us control the data bus until we have the NIOS processor up and running. The emulator takes input from the toggle switches and writes these to the AMVE data bus according to the Avalon bus specification. The Avalon bus is the bus used by Altera to interconnect SOPC devices. Bus reads are displayed on the 7-segment displays.



Goal
• Learn about sequential testbenches, response monitors and simulation modules • Learn about timing simulation and configurations • Get experience with structural VHDL.

Design


The ParallelBusEmulator has the following function:

• When the “read” button is pressed, an Avalon read-cycle is initiated. The read address is taken from the switches SW[15:8]. The upper four address bits is decoded to generate five chip select signals (CS[4:0]). The data read is displayed on the 7-segment displays HEX[1:0]. • When the “write” button is pressed, an Avalon write-cycle is initiated with the address and WrData set with switches SW[15:8] and SW[7:0] accordingly. • The bus interface matches that of an Avalon Memory-Mapped (Avalon-MM) interface. The emulator acts as an Avalon Master with fixed timing interface. See the Avalon Interface Specification section 3.5.2 and 3.10. Note that the bus master output signals are aligned to the positive clock edge. The line (4) shown in the slave figure is actually clock aligned when seen from the bus master.

Below is a slave timing diagram with WriteWaitTime = 2 & ReadWaitTime = 1




 * The bus clock frequency is 50 MHz.
 * Byteenable is NOT used since we only have an 8-bit interface.
 * Use the generics // WriteWaitTime // and // ReadWaitTime // to let the number of wait-states be adjustable.

=Exercises=

a) Create a testbench for the ParallelbusEmulator. The design file and additional files can be found in the excercise6.zip file.

The in the testbench you must do the following: 1. Create a 50MHz clock 2. A reset signal that goes high after 12 ns 3. Use the commands found in BrdSim.vhd to perform reads and writes (equal to use the slide buttons and key switches) o Ex. BrdWrite(X"06", X"53", BrdWr_n, BrdAddress, BrdWrData); 4. Create a separate process that monitors the Avalon bus. This process must output the values written and read on the Avalon bus (using the Report statement). 5. Add assertions to the process, to verify that timing requirements is met. 6. Test the design in ModelSim. Note the assertions. 7. Add the tinyRegister to your design and verify that you can now write to an address and read the value back.

b) Compile the design in Quartus and test the functionality on the DE2 board. 1. Open the Quartus project file (.qpf). compile the design. Note that the .qsf file is used by Quartus to store pin mapping etc. The qsf file is provided, so you don’t have to do the pinmapping your self – If the qsf file is placed in the project folder. 2. Note how the components are connected in the hierarchy. That the parallelbusemulator chip select 0 is mapped to a specific address 3. When successful, transfer the design to your board and verify