Registers+&+Memory+Map

=Memory Map=


 * **Board Address** || **Chip Select** || **Destination** ||
 * 0x00 – 0x0F || avs_s1_chipselects(0) || Tiny Register ||
 * 0x10 – 0x1F || avs_s1_chipselects(1) || Waveform generator ||
 * 0x20 – 0x2F || avs_s1_chipselects(2) || Codec Interface ||
 * 0x30 – 0x3F || avs_s1_chipselects(3) || Audio Switch ||
 * 0x40 – 0x4F || avs_s1_chipselects(4) || Echo Generator ||

=Registers=

Waveform Attenuation Register, **WA**
ATT- Attenuation The Waveform output is attenuated by the factor given in ATT: Waveform_out = Waveform_in / ATT Only attenuations dividable by two is allowed, that is, bit 0 is always read as zero.
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||| Reserved |||||||| ATT ||
 * RESET |||||||| 0 |||||||| 1 ||
 * R/W |||||||| W |||||||| W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

Waveform Frequency Register, **WF**
FREQ- Frequency The Waveform frequency is given by the value in FREQ according to the formula: FWaveform = 16384 / FREQ; If FREQ = 0, then FREQ=0x10, is used.
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||||||||||| FREQ ||
 * RESET |||||||||||||||| 0x10 ||
 * R/W |||||||||||||||| W ||
 * ADDR |||||||||||||||| Base Address + 0x1 ||
 * ADDR |||||||||||||||| Base Address + 0x1 ||

Codec Init Register, **CI**
INIT – Initialize Codec ‘0’: Do Nothing ‘1’: Initialize Codec
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||| Reserved |||||| Reserved || INIT ||
 * RESET |||||||| 0 |||||| 0 || 0 ||
 * R/W |||||||| W |||||| W || W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

Audio Source Codec Register, **ASC**
CODEC – Codec Audio Source 0x0: Mute (Audio = 0x000000) 0x1: AudioInFromCodec (Loopback) 0x2: AudioInfromWfm (Waveform Generator Output) 0x3: AudioInFromDsp (DSP Output) Other: Mute
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||| Reserved |||||||| CODEC ||
 * RESET |||||||| 0 |||||||| 2 ||
 * R/W |||||||| W |||||||| W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

Audio Source DSP Register, **ASP**
CODEC – Codec Audio Source 0x0: Mute (Audio = 0x000000) 0x1: AudioInFromCodec 0x2: AudioInfromWfm (Waveform Generator Output) Other: Mute
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||| Reserved |||||||| DSP ||
 * RESET |||||||| 0 |||||||| 0 ||
 * R/W |||||||| W |||||||| W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

Echo Delay Register, **ED**
DELAY – Delay Constant Delay between channels is: Tdelay = DELAY * 16 / 48 KHz => [0 < Tdelay < 8.5 ms]
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||||||||||| DELAY ||
 * RESET |||||||||||||||| 1 ||
 * R/W |||||||||||||||| W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

Echo Delay Update Register, **EDU**
UPD – Update Echo Coefficients 0x0: Do Nothing / Echo active 0x1: Update Coefficients
 * BIT || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
 * FIELD |||||||||||||| Reserved || UPD ||
 * RESET |||||||||||||| 0 || 0 ||
 * R/W |||||||||||||| W || W ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||
 * ADDR |||||||||||||||| Base Address + 0x0 ||

The register must be cleared again after updating the coefficients (written zero)

Example: Write (0x40, 0xFF) //Write ED register with new delay// //Write (0x41, 0x01)// Write EDU register to update coefficients Write (0x41, 0x00) // Write EDU register to let update take effect