Exercises_CombinatorialTestBench

=Introduction!= In order to test VHDL designs thoroughly, appropriate testbenches must be made. This exercise uses the 4-bit parallel adder created in previous exercises. For a brief introduction to ModelSim, read the “ModelSim Introduction” found on CampusNet->file sharing->docs. You should document your work, as the exam will be based on your exercise work. In ModelSim, waveforms can be exported with File->Export->Image.

=Goals=
 * Learn how to write a simple combinatorial Testbench
 * Get introduced to ModelSim
 * Learn how to write an intent model and use assertions.
 * Learn different approaches to test your design thoroughly.

=Parallel Adder Testbench= a) Design a basic testbench for the //4-bit Parallel Adder// design. The testbench only have to create the input signals. Validate the waveforms in ModelSim. Remember that the testbench is the new top design entity and that your 4-bit parallel adder design must be addes as a component in the new architecture

b) Write an intent model for the //4-bit parallel adder// design. The model must cover 10 input combination of the intent model. Add assertions to the testbench. Compare the 4-bit parallel adder outputs with the intent model output for the given input. Report an error if the result is invalid. Simulate in ModelSim and note the behaviour. Verify that it works by introducing an error in the intent model.

c) Write a functional test that uses arithmetic to estimate the output. Use assertions to compare estimate and UUT result.



d) Optional! Use the textIO functions to read the input simulation vectors from the “stimulus.dat” file provided. Validate the design with the assertions from (e). See the “ModelSim User’s Manual” page UM-71 for details on textIO.

**Note!** When you add “use std.textio.all” to your testbench and compile your design in ModelSim, the textIO library will appear in the simulation tab of the worksheet window. Clicking on this opens the package header file, and you’ll be able to see the function prototypes.

TextIO uses two functions for reading a file: code format="vhdl" readline(file, line);                   -- Reads a line read(line, bit/bit_vector/integer/etc.); -- Reads one element in                                        -- the line and moves the -- to the next element

code TextIO does not support std_logic, but does support “bit”. Conversion is done with: code format="vhdl"  := to_stdlogicvector();  := to_stdUlogic;

code

Stimuli files are commonly used when simulating with real-world data. But textIO is a weak spot of VHDL!!!